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Description: 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
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Size: 3184 |
Author: chenlei |
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Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。
-the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
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Size: 784543 |
Author: 东子 |
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Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
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Size: 19456 |
Author: 刘仪 |
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Description: 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
Platform: |
Size: 3072 |
Author: chenlei |
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Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。
-the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: |
Size: 784384 |
Author: 东子 |
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Description:
Platform: |
Size: 108544 |
Author: xinmuwang |
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Description: 本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。-The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.
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Size: 776192 |
Author: 黄虎 |
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Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
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Size: 1024 |
Author: 杨化冰 |
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Description: Verilog DLL sOURCE CODE
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Size: 7709696 |
Author: jc |
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Description: Clock DLL Block verilog source code
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Size: 104448 |
Author: jc |
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Description: HS DLL Verilog Module
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Size: 53248 |
Author: jc |
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Description: 该代码是为了配合VERILOG的测试，用C++模拟SPI4.2接口的时序功能，需要编译成.dll配合verilog仿真工具一起使用。-The code is in line with VERILOG test, using C++ simulation SPI4.2 interface timing functions, needs to be compiled into a. Dll with the verilog simulation tools.
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Size: 4096 |
Author: mb |
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Description: verilog model of a D-verilog model of a DLL
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Size: 10240 |
Author: aida yua |
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Description: 以crc7为例进行UVM的验证
Part 1：
搭建环境。
本文使用的Quartus II 13.1（64 bit），器件库MAX V。写了一个Verilog的简单的crc7。
仿真环境是ModelSim 10.2c。虽说自带UVM库。但是，没找到Modelsim自带的uvm_dpi.dll，于是，还重新编译了一番。
本文在win 10下。下载uvm-1.1d（现在最新版本有1.2d了），放好。(crc7 code by system verilog language)
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Size: 9063424 |
Author: viviergan |
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